1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device. More particularly, the present invention relates to a circuit and method for generating a write data mask signal in a synchronous semiconductor memory device.
This application claims the benefit of Korean Patent Application No. 10-2006-0003492, filed on Jan. 12, 2006, the disclosure of which is hereby incorporated by reference.
2. Description of Related Art
In general, a semiconductor memory device includes a matrix type memory cell array and reads/writes data from/to a particular memory cell in the memory cell array in accordance with certain control signals, such as read/write commands, a row address, a column address, etc.
The operating speed of conventional synchronous memory devices has historically been relatively low. This limitation precluded their use in high performance memory systems. More recently, however, the operating speed of synchronous memory devices, both single data rate synchronous DRAM (SDR SDRAM) or a double data rate synchronous DRAM (DDR SDRAM), has been significantly improved to the point where such devices may be incorporated into high performance memory systems.
Conventional SDR SDRAM input and output data on the rising or falling edge of a clock signal. In contrast, DDR SDRAM inputs and outputs data on both the rising and falling edges of a clock signal. Thus, factors other than clock speed not considered, DDR SRAM provide twice the data throughput of SDR SDRAM.
DDR SDRAM typically includes a data input mask pin (DM pin) adapted to mask data which need not be written. Accordingly, such data is not input when the write data mask signal is activated. In other words, when a write operation is performed and data in a specific “masked” memory cell is not changed.
Figure (FIG.) 1 is a circuit diagram of a conventional circuit 10 adapted to generate a write data mask signal useful in a synchronous memory device.
Referring to FIG. 1, the conventional write data mask signal generating circuit 10 includes an OR gate 11, an inverter 12, a NOR gate 13, a D latch 14, and an NMOS transistor 15.
D latch 14 latches a write data mask signal DM which is supplied from outside the synchronous memory device and is activated to a logic high level, in response to an internal clock signal CLK. D latch 14 outputs an internal write data mask signal DMO. The internal clock signal CLK is obtained by delaying an external system clock signal (not shown).
The internal write data mask signal DMO enables a memory cell to hold previous input data (or previously written data) instead of overwriting it with new data input through data input/output pins (DQ pins). In other words, the internal write data mask signal DMO controls a write data mask operation of the synchronous memory device.
For example, the internal write data mask signal DMO may deactivate a data input/output buffer included in a write data path or deactivate (or turn OFF) a column selection switch connected to a column selection line (CSL) included in an address path. The column selection switch selectively connects a bit line leading to the memory cell to an input/output line leading from a data input/output pin.
OR gate 11 generates a reset signal RST in response to a read signal RD or a write column disable signal CSLF_W.
NMOS transistor 15 resets (deactivates) the internal write data mask signal DMO from a logic high level to a logic low level in response to a reset signal RST.
Reset of the internal write data mask signal DMO is necessary when a write operation including a write data mask operation is completed and a read operation begins, because if the internal write data mask signal DMO is activated to a logic high level it will deactivate the data input/output buffer or the column selection switch used in the read operation, thereby interrupting the read operation.
The read signal RD indicates the read operation within the synchronous memory device and is delayed from an externally applied read command. Accordingly, in order to perform a read operation following a write data mask operation in the synchronous memory device, a write column disable signal CSLF_W is additionally used as the reset signal RST, because the internal write data mask signal DMO cannot otherwise be timely reset.
The write column disable signal CSLF_W indicates an activation end point of the column selection line signal generated when the write operation including the write data mask operation is performed. The column selection line signal controls the switching of the column selection switch.
The conventional write data mask signal generating circuit 10 resets the internal write data mask signal DMO when each individual write operation is completed. Accordingly, in a gapless write operation including a gapless write data mask operation in which a portion of the input data successively written through the data input/output pins is successively masked, the write data mask signal generating circuit 10 may not properly generate the internal write data mask signal DMO for the gapless write mask operation.
In particular, during an activation time interval of the write column disable signal CSLF_W, which enables the reset signal RST corresponding to the previous write data in the gapless write data mask operation to be generated, the internal write data mask signal DMO corresponding to current write data in the gapless write data mask operation is not activated. Accordingly, for the write data mask operation of the current write data, additional time is needed for deactivating the activated write column disable signal CSLF_W. This additional time restricts the operation of the gapless write operation and prevents high-speed operation of the synchronous memory device. The gapless write operation is included in the write operation and the gapless write data mask operation is not included in each individual data mask operation.